(1) Field of the Invention
The present invention relates to a fundamental logic circuit and, more particularly, to a high speed fundamental logic circuit used, for example, in an electronic computer.
(2) Description of the Prior Art
In a fundamental logic circuit such as an inverter or a NAND gate having an output inverter transistor whose emitter electrode is grounded, one of the most important factors influencing the operating speed of the fundamental logic circuit is the turn off time of the output inverter transistor. In order to reduce the turn off time of the output inverter transistor, it is necessary to quickly discharge the charge stored in the base region of the output inverter transistor.
FIG. 1 illustrates a TTL inverter circuit as an example of a conventional fundamental logic circuit which has an output inverter transistor. In FIG. 1, an input transistor Q.sub.1 is an NPN type transistor which switches current flowing from the positive voltage source V.sub.cc through a resistor R.sub.1 to the base electrode of the input transistor Q.sub.1 to an input terminal IN or to the base electrode of a driver transistor Q.sub.2. The driver transistor Q.sub.2 is an NPN type transistor which outputs both inverted and non-inverted signals of an input signal applied to the input terminal IN. An output inverter transistor Q.sub.3 is an NPN type transistor which is driven by an output signal from the emitter electrode of the driver transistor Q.sub.2. Transistors Q.sub.4 and Q.sub.5 are both NPN type transistors which constitute a Darlington transistor driven by an output signal from the collector electrode of the driver transistor Q.sub.2. The transistor Q.sub.5 serves as a level shift circuit which provides a potential difference between the emitter electrode of the transistor Q.sub.4 and the collector electrode of the output inverter transistor Q.sub.3, i.e., the output terminal OUT, and the level shift circuit can be replaced by a diode connected therebetween. The output inverter transistor Q.sub.3 and the Darlington transistor consisting of the transistors Q.sub.4 and Q.sub.5 constitute an output stage having a so-called totem-pole structure.
The TTL inverter circuit of FIG. 1 is well known and, therefore, the general description of the operation thereof is omitted herein, and the operation thereof will be described for a condition wherein the output potential of the output terminal OUT changes from low (i.e. about 0.4 V) to high (i.e. about 3.4 V, which is the potential of the voltage source V.sub.cc -2 V.sub.BE). When the potential of the input terminal IN changes from high to low, the driver transistor Q.sub.2 changes from the turned on condition to the turned off condition. Therefore, the potential of a point A, i.e., the collector electrode of the transistor Q.sub.2 changes from low to high, and the potential of the emitter electrode of the transistor Q.sub.2 changes from high to low. Accordingly, the transistor Q.sub.3 begins to change from the turned on condition to the turned off condition. However, turning off of the transistor Q.sub.3 is not complete until the base charge stored in the base region of the transistor Q.sub.3 is discharged and the transistor Q.sub.3 remains in the turned on condition until the base charge is completely discharged. In order to discharge the base charge stored in the base region of the transistor Q.sub.3, a resistor R.sub.5 is connected between the base electrode and the emitter electrode (i.e. the ground) of the transistor Q.sub.3, so that a discharge path is constituted. Therefore, although the discharge time of the base charge can be reduced by decreasing the resistance value of the resistor R.sub.5, it is impossible to greatly decrease the resistance value of the resistor R.sub.5. This is because, when the transistor Q.sub.3 is turned on, the resistor R.sub.5 provides a bypass for the base current of the transistor Q.sub.3 to the ground, and if the resistance value of the resistor R.sub.5 is very small, the base current becomes too small to turn on the transistor Q.sub.3 completely. Therefore, in the logic circuit of FIG. 1, the turn off time of the output inverter transistor Q.sub.3 cannot be very small.
Moreover, the conventional logic circuit of FIG. 1 has the disadvantage of having a poor transfer characteristic as shown in FIG. 2. Assume that the input potential V.sub.IN of the input terminal IN increases from low to high gradually. When the input potential V.sub.IN increases in the range from V.sub.BE2 to V.sub.BE2 +V.sub.BE3, the potential of the base electrode of the driver transistor Q.sub.2 also increases from V.sub.BE2 to V.sub.BE2 +V.sub.BE3. Wherein, V.sub.BE2 designates the base-emitter voltage of the transistor Q.sub.2 and V.sub.BE3 designates the base-emitter voltage of the transistor Q.sub.3. In this condition, the driver transistor Q.sub.2 begins to change from the turned off condition to the turned on condition, so that the current passing through a resistor R.sub.2, the main current path of the driver transistor Q.sub.2 and the resistor R.sub.5 increases gradually. In this condition, the potential of the point A, i.e., the collector electrode of the driver transistor Q.sub.2, falls gradually and, therefore, the potential of the output terminal OUT falls gradually. This is because the transistors Q.sub.4 and Q.sub.5 are in the turned on condition and the output inverter transistor Q.sub.3 is still in the turned off condition, and the potential of the point A is transferred to the output terminal OUT through the base emitter junctions of the transistors Q.sub.4 and Q.sub.5. Therefore, in the input potential range from V.sub.BE2 to V.sub.BE2 +V.sub.BE3, the transfer characteristic of the conventional logic circuit is not sharp as illustrated in FIG. 2. After the input potential V.sub.IN becomes larger than V.sub.BE2 +V.sub.BE3, the inverter transistor Q.sub.3 turns on and the output potential V.sub.OUT falls to a low level (i.e. about 0.4 V) quickly.
FIG. 3 illustrates a two input DTL NAND gate circuit as another example of a conventional fundamental logic circuit. The circuit of FIG. 3 comprises a diode gate consisting of Schottky barrier diodes (hereinafter referred to as SBD), D.sub.31 and D.sub.32, and a resistor R.sub.31. Transistors Q.sub.34 and Q.sub.35, which constitute a Darlington transistor, are driven by an output signal from the collector electrode of a driver transistor Q.sub.32, and an output inverter transistor Q.sub.33 is driven by an output signal from the emitter electrode of the driver transistor Q.sub.32. The Darlington transistor consisting of the transistors Q.sub.34 and Q.sub.35, and the output inverter transistor Q.sub.33 constitute a totem-pole output stage. The NAND gate circuit of FIG. 3 also comprises a switching transistor Q.sub.36 in order to quickly discharge the base charge stored in the base region of the output inverter transistor Q.sub.33, so that the turn off time of the transistor Q.sub.33 is reduced. The base electrode of the switching transistor Q.sub.36 is connected to the collector electrode of the driver transistor Q.sub.32 through diodes D.sub.33 and D.sub.34, and to the ground through a resistor R.sub.35.
Operation of the switching transistor Q.sub.36 will now be described. When the input potential V.sub.IN1 and V.sub.IN2 of both input terminals IN.sub.1 and IN.sub.2 are high, the driver transistor Q.sub.32 is turned on and the output inverter transistor Q.sub.33 is turned on. Therefore, the potential of the collector electrode of the driver transistor Q.sub.32 is low, so that the transistors Q.sub.34 and Q.sub.35 are both turned off and the potential of the output terminal is low. In this condition, the diodes D.sub.33 and D.sub.34 are turned off, and therefore, the switching transistor Q.sub.36 is turned off.
Assume that the input potential of at least one of the input terminals IN.sub.1 and IN.sub.2 changes to low, then the driver transistor Q.sub.32 turns off so that the potential of the collector electrode of the transistor Q.sub.32 becomes high. Therefore, the transistors Q.sub.34 and Q.sub.35 are turned on, and the output inverter transistor Q.sub.33 is turned off. In this condition, current flows from the collector electrode of the driver transistor Q.sub.32 through the diodes D.sub.33 and D.sub.34 to the base electrode of the switching transistor Q.sub.36, and to the ground through a resistor R.sub.35. Therefore, the switching transistor Q.sub.36 turns on and quickly discharges the base charge stored in the base region of the output inverter transistor Q.sub.33, so that the turn off time of the output inverter transistor Q.sub.33 is reduced.
However, the conventional logic circuit of FIG. 3 has the following disadvantages.
(1) The threshold voltage V.sub.TH of each of the input potentials V.sub.IN1 and V.sub.IN2 is as follows. EQU V.sub.TH =V.sub.CE36 +V.sub.BE32 -V.sub.F .apprxeq.0.8 V (1)
Where V.sub.CE36 is a saturated collector-emitter voltage (i.e. about 0.4 V) of the switching transistor Q.sub.36, V.sub.BE32 is a base-emitter voltage (i.e. about 0.8 V) of the driver transistor Q.sub.32 and V.sub.F is a forward biased voltage (i.e. about 0.4 V) of the diode D.sub.31 or D.sub.32. Therefore, the threshold voltage V.sub.TH becomes about 0.8 V, and is smaller than that of a usual TTL gate circuit, so that the logic circuit of FIG. 3 has a poor noise immunity.
(2) The current flows from the positive voltage source V.sub.cc through the resistor R.sub.32, the diodes D.sub.33 and D.sub.34, and the resistor R.sub.35 and the base-emitter junction of the switching transistor Q.sub.36 to the ground all the time the driver transistor Q.sub.32 is in the turned off condition. Therefore, the power consumption of the logic circuit is large.
(3) The logic circuit of FIG. 3 uses a large number of semiconductor elements and, therefore, the circuit occupies a relatively large area in an integrated circuit.
Examples of a prior art fundamental logic circuit having an output inverter transistor are disclosed in the publication "The TTL Data Book for Design Engineers" First Edition, by Texas Instruments Incorporated, 1973, P. 87 or P. 89.